The increasing complexity of microprocessor chips has led to single chips containing several devices. These devices include one or more of the following: a processor core, cache memory, input/output circuitry, graphics processors, etc. Conventional communication between on-chip devices using dedicated busses has given way to on-chip interconnection networks (“OCINs”). OCINs use network communication pathways and routers on the chip to direct data between on-chip devices. This data may be in packets, with each packet divided into smaller flow control digits (abbreviated as “flits”).
Traditionally OCINs incorporate routers with buffers, in order to maximize bandwidth efficiency. Unfortunately, these router buffers introduce several serious drawbacks at the small scale of a single chip. First, router buffers consume significant amounts of power, even when not storing data. This power consumption not only is wasteful of electrical energy, but also increases heat dissipation of the chip. Second, using buffers increases the complexity of the network design by requiring logic circuitry to handle the buffering. Finally, buffers consume significant amounts of valuable surface area on the chip itself, reducing the available for other uses.
Thus, there is a need for an OCIN which does not require the use of buffers.